String to path conversion

SystemVerilog
1 

module csm
logic [3:0] sel;
integer vg [3:0][4:0];
----code------
endmodule

module fsm

csm (----porting done-----); // Also uses vg to do some calculation


module testbench ();
integer tb_vg [3:0] [4:0];

/* I need help here */

Right now, I have hardcoded and assigned the entire array from DUT to test bench.
However, I want to assign vg on the fly like this integer tb_vg = fsm.csm.vg [sel];
My current modification is:
Using a `define macro, doing str2pa (x) ``x

So I have created a string and sformat it,
$sformat (ab, “fsm.csm.%d”, sel);
tb_vg = `str2pa(ab);

However this is issuing an error saying string to unpacked is not allowed.

Help is much appreciated.

2

This isn’t how programming languages generally work. You can’t just take a string and convert it into a path to a variable. You need reflection for this.

Verilog and SystemVerilog provide a mechanism for this, called the Verilog Programming Interface (VPI). This allows you to interrogate the underlying simulation model using strings. You can find more info in the LRM. Also, simulator vendors usually provide util functions that do what you want. For QuestaSim, if I remember correctly, it’s called $init_signal_spy(…). You’ll find more info in the user manual.