for default scenarios :
class is always dynamic type but can i declared static type class :
i.e
static class A;
int a;
function void disp();
$display(“Class A”);
endfunction
endclass
is this valid example if not than why it's not possible or is there other way to do this things???????????
In reply to mrudang pujari1:
There are no static classes in SystemVerilog. SystemVerilog was patterned after Java, which does not have atatic classes as well (except for a special case with nested inner classes)
If you could declare a static class, there would be too many restriction on its use. This arises because there is no longer a separation between the class type and the class objet. This means there would be no way to extend or parameterize a static class. And there would be no way to pass a handle to another class variable (or an argument of a method) because there is no type to associate with the class variable.
SystemVerilog could probably invent additional mechanisms to deal with these issues, but then what is the benefit of a static class in the first place? You can achieve similar functionality by declaring a class with all of its members and methods act static.
There is no concept of static class in sv.
instead you can have static method , variable in side class