Signedness via parameters

SystemVerilog
1

I have a class:

    class t_Complex #(parameter int W);
        bit signed [W-1:0] Re;
        bit signed [W-1:0] Im;
    endclass

But I want not only the width W via a parameter, but also the signedness (i.e. a class that con contain either signed or unsigned complex numbers). Is this possible?

2

Use a type parameter.

3

You mean like:

 class t_Complex #(type T, parameter int W);
        T [W-1:0] Re;
        T [W-1:0] Im;
 endclass

...

t_Complex#(bit signed, 20)=new;

?

I thought of that, but it feels a bit weird, it allows to give any type and I actually only needed the choice between signed/unsigned. Some of my code probably relies on T being a signed or unsigned bitvector. But if this is the only way to do it…so be it…

4

In reply to NiLu:

I was actually thinking of using T to represent the entire type: ‘bit signed [W-1:0]’