@ Signal not working as expected

Hi,
I have the following code in my testbench:

" uvm_info (get_name(), "In For loop", UVM_LOW); @(m_ctlr_intf.bfm_cb); uvm_info (get_name(), “In For loop after delay”, UVM_LOW);"

For this my Expected behaviour is below:
" @ 1000: uvm_test_top.ecc_env.m_qcmem_ctlr_agent[1].driver [driver] In For loop
@ 1200: uvm_test_top.ecc_env.m_qcmem_ctlr_agent[7].driver [driver] In For loop after delay" -Here , 200 is the cycle gap.
But some times second print statement is printing along with first print like below:
" @ 1000: uvm_test_top.ecc_env.m_qcmem_ctlr_agent[1].driver [driver] In For loop
@ 1000: uvm_test_top.ecc_env.m_qcmem_ctlr_agent[7].driver [driver] In For loop after delay"

Could you please help me to solve this or any alternate method to achieve this behaviour.

–Thanks

In reply to karunakarG:
See this discussion
https://verificationacademy.com/forums/uvm/no-time-pass-after-xxxcb#reply-62195