Shift operator and power operator in systemverilog coverage

SystemVerilog
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1

Hi,

Following is my coverage code:

covergroup cov,

addr: coverpoint <signal_name>{
 bins a1 = 6'h0;
 bins a2 =6'h1;
 .
 .
 .
 bin a63 = 6'h3f;
}

byte_en: coverpoint <signal_name2>{
 bins b1 = 64'h1;
.
.
.
.
bins bn = 64'hfffff....ff;
}

addr_byen : cross addr, byte_en{
  ignore_bins i1 = addr_byen with (byte_en < (1<<(addr)));
}

endgroup

when I use this , my simulations gets stuck forever. Even the same happens with power(**) operator.
The moment I remove << operator or ** operator and simply put (byte_en < addr), it goes well.
I dnt face this issue with other arithmetic and logical operators.

Where am i going wrong?