SE: SystemVerilog keyword 'class' is not expected to be used in this context

SystemVerilog
,
1

Hello all,
I have gone through same syntax error asked by someone in UVM forum but I am facing the same in SystemVerilog. As suggested in that forum I have included everything into a package and tried to run but same error is persisting. Please help me in resolving this error. I am posting my package.sv file here so that you can find anything fishy in it.

package pkg;
include "transaction.sv" include “generator.sv”
include "driver.sv" include “monitor_in.sv”
include "monitor_out.sv" include “assertions.sv”

include "scoreboard.sv" include “env.sv”
`include “test.sv”

endpackage

I have included this package.sv file in top.sv file. I sincerely thank you in advance.

2

In reply to Ram@12:

Usually problems like these are because of the line that proceeds it. Is this the very first occurrence of a class?

3

In reply to dave_59:

I am getting as “class” not expected in the first line of generator.sv after parsing transaction.sv. And I have run the same code without package in EDA it was working fine. But in tool it is showing this.

4

In reply to Ram@12:

You either created a problem when you transferred the code to your local environment, have a scripting issue, or run into a tool specific problem.