Sampling the inputs of an interface with the value of what is present at the clock edge

SystemVerilog
,
1

Hi,
I have an interface without a modport or clocking block like:

interface(
logic a,
logic b,
logic result
);

assign result = a+b;

endinterface
Is it possible to have an interface without modport or clocking block?

I’m primarily looking at finding the value of result in the same clock cycle as when I drive a and b

From my uvm agent (which has a virtual handle to this interface), if i drive a and b, i want to immediately access result . Can you please let me know how it can be made possible.

Thanks

2

In reply to Ramyas:

You certainly don’t need to use modports in your testbench. There are mainly for design.

You don’t need clocking blocks either. have you tried accessing “result” directly from your virtual interface? The only recommendation I have is once you start using clocking blocks with a set of clocking variables, don’t mix the use of clocking blocks with the direct signals.