Same always statement executed twice on same time

SystemVerilog
,
1

Dear Forum,

Can you please help debug to one strange issue that I see. This is part of my code from the big behavioral model:

 always @( posedge CLK or negedge CLK ) begin
            $display ("%t: %m: always execution", $time);
   end

And this is simulation result on QuestaSim:

149.000ns: TB.GLD_C0: always execution
149.000ns: TB.GLD_C0: always execution
150.000ns: TB.GLD_C0: always execution
150.000ns: TB.GLD_C0: always execution
151.000ns: TB.GLD_C0: always execution
151.000ns: TB.GLD_C0: always execution
152.000ns: TB.GLD_C0: always execution
152.000ns: TB.GLD_C0: always execution
153.000ns: TB.GLD_C0: always execution
153.000ns: TB.GLD_C0: always execution
154.000ns: TB.GLD_C0: always execution
154.000ns: TB.GLD_C0: always execution
155.000ns: TB.GLD_C0: always execution

You can see that each time is repeating twice, or in other word the always statement executed 2 times for each time.
I think this issue is connected with some races in the behavioral model, however I cannot understand what is going on and how to debug this issue.

Can someone please provide some hints about how I can debug this issue, understand why the code behaves like this.

Thanks
Hayk

2

In reply to haykp:

Try using $realtime instead of $time.

3

In reply to dave_59:

With $realtime I can see the difference

149.000ns: TB.GLD_C0: always execution
149.500ns: TB.GLD_C0: always execution
150.000ns: TB.GLD_C0: always execution
150.500ns: TB.GLD_C0: always execution
151.000ns: TB.GLD_C0: always execution
151.500ns: TB.GLD_C0: always execution
152.000ns: TB.GLD_C0: always execution
152.500ns: TB.GLD_C0: always execution
153.000ns: TB.GLD_C0: always execution
153.500ns: TB.GLD_C0: always execution
154.000ns: TB.GLD_C0: always execution
154.500ns: TB.GLD_C0: always execution
155.000ns: TB.GLD_C0: always execution

So $time rounds the value, while $realtime doesnt.

4

In reply to haykp:

which means your clk period is 1ns