Regular Expressions Usage in SV

SystemVerilog
1

Hi,

I want to evaluate a string s1 which might have either of two strings s2 or s3 or both using Regular expressions as shown

s1 = "important";
s2 = "ant";
s3 = "port"

result = uvm_pkg::uvm_re_match("*(ant|port)*",s1);

In the above code, Iam getting runtime errors.
reporter [UVM/DPI/REGEX_INV] uvm_re_match : invalid glob or regular expression:
|Invalid preceding regular expression|

Please help me out with proper code.

Thanks
AJ

1 Like
2

In reply to Anudeep J:
Use “(ant|port)” without the *'s

A good site to debug regular expressions is https://regex101.com

3

In reply to dave_59:

Thanks for the reply Dave. It is working.