Reg field by name

SystemVerilog
1

Hi,

I am creating a subroutine to basically peek a register name by field : How can i achieve that ?


task peek_reg_name_field;
input string reg_name;
input string field_name;
output [31:0] data;
begin 
    case(reg_name);
    CTRL : data  = `PKG.data;
endcase 
end 
endtask 

Now CTRL has many fields now (ex: X, Y, Z ) 1 bit wide, How do i change this to support by field name 

TIA
2

In reply to tejasakulu:

If asking this kind of approach seems like you cannot leverage the ral model. Anyway one approach is to use defines in a local file that you include:

define x 0:3 define y 4:10
…

Then you need add a switch used to select between reg_name and reg_field.

  1. If the reg_field is selected then you will do:
    Case(field)
    X: data = path.data[x];
    …

Alternatively you could wrap around everything in a task which let you use it everywhere as some utilities.

Sorry if i did not use the Systemverilog tag but I’m with phone. Regards