Hello,
We developed macro based SV Assertions in block 1 and trying to use those in block2. However we were encountering errors while we use them in block2. I have highlighted the lines that has the errors in bold.
May I pls know if we are missing anything here, should we have to use the default clocking or $inferred_clk ?
// block1 rough code below
import uvm_pkg::*;
`include "uvm_macros.svh"
module block1_bind
(input wire clk,
input wire rst_n,
input wire mc_clk,
input wire mc_rst_n,
input wire block1_pclk,
input wire block1_prst_n,
input wire block1_sig_rderr
);
string report_id = "block1_bind";
//////////////////////////////////////////////////////////////
//output signal shouldn't be driven with x value
//////////////////////////////////////////////////////////////
property p_check_signal_x(clk_arg, reset_arg, signal_arg);
@(posedge clk_arg) disable iff(!reset_arg)
$isunknown(signal_arg) == 0;
endproperty: p_check_signal_x
`define check_signal_x(clk_arg, reset_arg, signal_arg)\
assert property(p_check_signal_x(clk_arg, reset_arg, signal_arg))
`define check_signal_x_cover(clk_arg, reset_arg, signal_arg)\
cover property(p_check_signal_x(clk_arg, reset_arg, signal_arg))
A_signal_x_check: `check_signal_x(clk, rst_n, block1_sig_rderr);
c_signal_x_check: `check_signal_x_cover(clk, rst_n, block1_sig_rderr);
//////////////////////////////////////////////////////////////
//clock period check
//////////////////////////////////////////////////////////////
property p_clock_period_check(clk_arg, time clock_period);
time current_time;
@(posedge clk_arg)
(('1, current_time = $time) |=> (clock_period == $time-current_time));
endproperty: p_clock_period_check
`define clock_period_check(clk_arg, clock_period)\
assert property(p_clock_period_check(clk_arg, clock_period))
`define clock_period_check_cover(clk_arg, clock_period)\
cover property(p_clock_period_check(clk_arg, clock_period))
`define clock_x_check(clk_arg)\
assert #0 ($isunknown(clk_arg) == 0)
`define clock_x_check_cover(clk_arg)\
cover #0 ($isunknown(clk_arg) == 0)
A_clock_x_check: `clock_x_check(clk)
else
$error(report_id, $psprintf("%t block1 Clock driven with X", $time));
//c_clock_x_check: `clock_x_check_cover(clk);
c_clock_x_check: `clock_x_check_cover(clk) $display("%t block1 Clock not driven with X", $time);
/// ***
// block 2 rough code below
`include "block1_bind.sv"
import uvm_pkg::*;
`include "uvm_macros.svh"
module block2_bind
(input wire clk,
input wire rst_n,
input wire block2_clnt0_wcrdt
);
string report_id = "block2_bind";
**A_block2clock_period_check: `clock_period_check(clk, 2.0ns)
** else
$error(report_id, $psprintf("%t Clock period not correct for block2 CLK", $time));
**c_block2clock_period_check: `clock_period_check_cover(clk, 2.0ns) $display("%t Clock period correct for block2 CLK", $time);
**
**A_block2signal_x_check: `check_signal_x(clk, rst_n, block2_clnt0_wcrdt)**
else
$error(report_id, $psprintf("%t block2 rderr driven with X", $time));
**c_block2signal_x_check: `check_signal_x_cover(clk, rst_n, block2_clnt0_wcrdt) $display("%t block2 rderr not driven with X", $time);
**
initial begin
$display("INFO: block2 assertion bind file loaded");
end
endmodule: block2_bind
///Error msg encountered:
** Error (suppressible): repo_0411/rtl/binds/block2_bind.sv(36): (vlog-1957) The sva directive is not sensitive to a clock. Unclocked directives are not supported.
** Error (suppressible): repo_0411/rtl/binds/block2_bind.sv(41): (vlog-1957) The sva directive is not sensitive to a clock. Unclocked directives are not supported.
** Error (suppressible): repo_0411/rtl/binds/block2_bind.sv(45): (vlog-1957) The sva directive is not sensitive to a clock. Unclocked directives are not supported.
** Error (suppressible): repo_0411/rtl/binds/block2_bind.sv(50): (vlog-1957) The sva directive is not sensitive to a clock. Unclocked directives are not supported.
rgds
Kishore