In the recent developements of SV,multiple inheritence has been included.From where should i read more about this topic.Also i need to know more about global clocking.
In reply to sougata_asic:
You should see this paper 8.2: Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 – it won the best paper at this year’s DVCon
and check out the second best paper 5.1 SystemVerilog Interface Classes - More Useful Than You Thought
In reply to dave_59:
Unfortunately, the link of first paper is not working. I am talking about this paper.