Randomization with X and Z

SystemVerilog
1

Hi,

may i know how to randomize a single and multibit variable to get X or Z along with 0 and 1 to its value, Thanks in advance.

Regards
k venkatesh

2

In reply to kathula venkatesh:

randomization gives only 2-state value i.e a bit would be either 0 OR 1 .
( Even if you declare variable as :: rand logic !! )

You would have to write some logic in post_randomize() .
I have seen code with randsequence too

3

In reply to Have_A_Doubt:

Something like

class some_class;
  
  parameter int WIDTH = 8;
  
  logic [WIDTH - 1:0] a;
  rand bit [1:0] a_temp [WIDTH - 1:0];
  
  function void post_randomize; 
    for (int index = 0; index < WIDTH; index++) begin
      case (a_temp[index])
        2'd0 : a[index] = 1'b0;
        2'd1 : a[index] = 1'b1;
        2'd2 : a[index] = 1'bz;
        2'd3 : a[index] = 1'bx;        
      endcase
    end    
  endfunction : post_randomize 
  
endclass : some_class