Randomization of Register Address and Data

SystemVerilog
,
1

Hello,

I have a AHB Agent connected to DUT.
DUT has around 100 blocks with different Registers.
There is a RegModel instantiated in the UVM Testbench.
Which Registers are writable and which are not are
in the RegModel. When sending Random Address and Data from the AHB Agent,
how will it know which bits are Writable and which are not ?
Is there a way to Read the RegModel and Randomize accordingly
or there is a Separate Randomization test in the RegModel itself
which can be called.
How does the Register Randomization work ?

class ahb_transaction extends uvm_sequence_item;
  `uvm_object_utils(ahb_transaction)
  //typedef for READ/Write transaction type
  typedef enum {READ, WRITE} kind_e;
  rand bit   [31:0] addr;      //Address
  rand bit [31:0] data;     //Data - For write or read response
  
  constraint c1{addr[1:0] =2'b0; addr[31:0]>=32'd4000_0000; addr[31:0] <32'd5000_0000;};
  constraint c2{data[31:0]>=32'd0; data[31:0] <32'd256;};
endclass

JeffD

2

In reply to dvuvmsv:

If your register model maps the entire AHB address space, then you typically would use the register model instead of sending aha_transaction items directly.

Yes, there are built-in tests for writable registers.

See
https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_access_seq-svh.html