Randomization: I am trying to randomize some data members, but not able to see random behavior if I run it for just one time

SystemVerilog
1

I am trying to randomize some data members, I encountered that if I don’t do .randomize() in a repeat loop, I don’t see random behavior on my rand data members. Can anyone please help me out here.

Below is my code

Thanks

// Code your testbench here
class avmm_param;

   typedef enum {user_mode} support_mode;
   //engineering_mode
   typedef enum {duplex,tx,rx} duplex_mode;

   rand support_mode protocol_support_mode;
   rand duplex_mode transceiver_mode;
 
  function void display_params();
      $display("****************Randomized Parameters********************");
      $display("support_mode is %s \n", protocol_support_mode);
      $display("duplex_mode is %s \n",transceiver_mode);     
  endfunction
endclass

module param_config ();
   
   initial begin
      avmm_param avmm_config_inst = new();

    // repeat (5) begin If I remove the repeat loop, I am not able to see random behavior everytime I compile this file. If I add repeat loop than I see random behavior
       if (avmm_config_inst.randomize())  avmm_config_inst.display_params();
	 else $error("Randomization Failed \n");
  //   end
   
   end

endmodule
2

In reply to Karmapanchal:

Random stability is a feature of SystemVerilog that allows you to repeat the exact random values every time you run the tool for debugging and to see if RTL fixes can pass with the same test.

To get different random values for each run of your tool, you need to change the seed, or specify a random seed. Check your tool documentation for “random seed”

3

In reply to dave_59:

Thanks Dave :) , I got the point now.