Random Variables as indexes in Constraints

SystemVerilog
,
1

Based on LRM :: " Index expressions can include loop variables, constants, and state variables. Invalid or out-of-bounds array indices are not automatically eliminated; users must explicitly exclude these indices using predicates. "

So this tells me that random variables can’t be used as indexes .


// CODE I
class Main ;

   rand bit[1:0] index ;
   rand bit[2:0] val[] ;

  constraint SIZE { val.size() == 4 ; }

  constraint VAL {
                    foreach(val[i])
                   if ( i == index )
                    val[index] == ( i+index) ; // [A] :: 'index' a random variable is being used as index !!
                 }

 endclass

Main m  ;

 initial begin

 m = new() ;

 if ( m.randomize() )
  begin
    $display("Success with %p",m);
  end

 end

The Output of above code is ::

Success with ‘{index:2, val:’{0, 6, 4, 7}}

Similarly I have CODE 2 where I ONLY change index to an unpacked array


  // CODE 2
class Main ;

   rand bit[2:0] index[] ; // Changed to unpacked array from CODE I
   rand bit[2:0] val[] ;
 
  constraint SIZE { val.size() == 4 ; index.size() == 4 ; } 

  constraint VAL { 
                    foreach(index[i])
                   {
                     index[i] inside {[0:3]} ;

                   }

                    foreach(val[i])
                    val[index[i]] == ( i+index[i] ) ;  // **:: index[i] i.e element of index array used as index !!
     
                 }

 endclass

This gives me Output

[b]Success with ‘{index:’{3, 0, 2, 1}, val:'{1, 4, 4, 3}}**

[Q] Am I missing something here ? Shouldn’t [A] && [B] be a randomization failure / Compilation issue ?

2

In reply to TC_2017:

Yes, this is a current restriction in the LRM. But tools have relaxed certain cases, leaving the LRM and the users trying to understand it behind. I hope to fix that soon.