Random in time register read -SV

[xfinity]

Hello Everyone,

I have requirement to do polling i.e, i should do random register read of the interrupt register. How do i randomly do register read in random time. Any pointers do i need to use rand or any suggestions.

PS: I have task READ_REG(INTR) which reads the interrupt register, how do i do this read in random time

Thanks,
Tejas

[ben2]

In reply to tejasakulu:
Randomize an int variable and Delay that variable. Randomize the reg number.

 import uvm_pkg::*; `include "uvm_macros.svh" 
module top;      
    event e; // for debug  
    function void READ_REG(int q) ;
        -> e; 
    endfunction 

 initial begin 
        int v, r; 
        repeat(200) begin  
            if (!randomize(v, r)  with 
            { v < 40 && v > 10; 
              r < 16 && r >= 0; 
        }) `uvm_error("MYERR", "This is a randomize error");
        #v; 
        READ_REG(r);
        end 
        $stop; 
   end  
endmodule  
 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

---

1. SVA Alternative for Complex Assertions
   Verification Horizons - March 2018 Issue | Verification Academy
2. SVA: Package for dynamic and range delays and repeats | Verification Academy
3. SVA in a UVM Class-based Environment
   SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy