Race conditions in verilog

SystemVerilog
, ,
1

Hi all,

I am having a doubt regarding execution of statements in verilog. In below code at time 2 in tb module,there are 2 blocks having 1 statement each will be having a race condition and if clk executes first then always block in dff module will be executed and in which region does the @() executes. how this works kindly explain it to me.
thank you.

module dff(d,clk,q);
  
  input d,clk;
  output reg q;
  
  always@(posedge clk)
    begin
      q = d;
    end
endmodule

module tb;
  
  reg d,clk= 0;
  wire q;
  
  dff a1(d,clk,q);
  initial
    begin
      repeat(10)
        #2 clk = ~clk;
    end
  
  initial
    begin
       d = 0;
      #2 d = 1;
      #4 d = 0;
    end
  
  initial
    begin
      $dumpfile("test.vcd");
      $dumpvars(0,tb);
    end
endmodule
2

In reply to sasi_8985:

In your code, you are trying to write d=1 at T=2 and also, reading its value via q at T=2 for the first time. So, this is a race-condition. To avoid such cases, you can use non-blocking assignments and try to assign the value of d somewhat prior to triggering clock edge.

@ based events are executed in active region as are all other constructs. Think of @ as a scheduler, which waits for a change to happen.

3

In reply to chiranjeev:

In reply to sasi_8985:
In your code, you are trying to write d=1 at T=2 and also, reading its value via q at T=2 for the first time. So, this is a race-condition. To avoid such cases, you can use non-blocking assignments and try to assign the value of d somewhat prior to triggering clock edge.
@ based events are executed in active region as are all other constructs. Think of @ as a scheduler, which waits for a change to happen.

thanks :-)