Question about system verilog property statement

SystemVerilog
1

Hi,
I have a question about SV property syntax as follows :
LRM 1800- 2012 specifies following syntax for property :

property_declaration ::=
property property_identifier [ ( [ property_port_list ] ) ] ;
{ assertion_variable_declaration }
property_spec [ ; ]
endproperty [ : property_identifier ]
property_port_list ::=
property_port_item {, property_port_item}
property_port_item ::=
{ attribute_instance } [ local [ property_lvar_port_direction ] ] property_formal_type

property_spec ::=
[clocking_event ] [ disable iff ( expression_or_dist ) ] property_expr

Can we have multiple property spec statements in a property statement. Property statements i have seen in SVA Assertions Handbook have only single property spec statement.

regards,
-sunil puranik

2

In reply to puranik.sunil@tcs.com:

The BNF clearly shows one property_spec per property_specification.

BTW, the IEEE 1800-2017 SystemVerilog LRM is current.

3

Thanks Dave for the reply. But why should this requirement of one spec per property be there?
rgs,
-sunil

4

In reply to puranik.sunil@tcs.com:

Think of a property as a function that returns true or false each clocking event. What would it mean to have multiple function bodies in one function declaration, especially if they had different clocking events? Perhaps you could explain the functionality you were looking for that you can’t seem to achieve with the existing syntax.