Can anyone tell me what is wrong with this concatenation? I dont see the data_in propagating to data_out for some reason.
// Code your design here
module shift_register (input clk,data_in,rst,output final_op);
reg [4:0]data_out;
always @ (posedge clk or negedge rst) begin
if (!rst)
data_out <= '0;
else
data_out<= {data_out[4:1],data_in};
end
assign final_op = (data_out==10110)?1:0;
endmodule
// Code your testbench here
// or browse Examples
module tb;
reg clk,data_in,rst,final_op;
wire [4:0] data_out;
shift_register s1(.*);
initial begin
$dumpfile(“dump.vcd”);
$dumpvars;
fork begin
clk=0;
rst =0;
data_in=0;
#5 rst=1;
#5 rst=0;
#3 data_in=1;
#5 data_in=0;
#3 data_in=1;
end
begin
repeat (100)
clk = #1 !clk;
end
join
end
endmodule