Hello ,
why still rtl design code is still written in verilog eventhough system verilog has more features and more features .can any one please know the apt reason which would be really helpful
In reply to venky970:
Yes, it seems very strange. People have no problem replacing their cellphone every 2 years to get the latest and greatest technology, but when it comes to designing those products, those same people are still stuck in the 90’s (Verilog 1995 and VHDL 1993).
Two major reasons why SystemVerilog adoption has been slower than some would like to see
- Legacy designs. Most designs don’t start from scratch. People take existing code and modify it
- Tool support - especially FPGA synthesis tools. There are many tools involved in the design flow and if one the tools in your chain does not support one feature, and another tool does not support a different feature, then you’re more likely to just stay with Verilog than try to navigate around it.
But those scenarios have been gradually changing over time and SystemVerilog is posed to take over Verilog for ASIC design in the next 2 or 3 years. See this 2020 Functional Verification Study that shows the trends in choice of languages for design.