Passing mailbox array member to module by reference

SystemVerilog
1 

parameter NUM_DEVICES = 24;

mailbox #(byte) expected_bytes [NUM_DEVICES];
mailbox #(byte) test;
generate 
for(genvar g = 0; g < NUM_DEVICES; g++) begin:device_block
   my_module test(.expected_bytes(expected_bytes[g]);
end

module my_module(
ref mailbox #(byte) expected_bytes
);

Hi,

I have the above code where I want to pass in a mailbox from an array of mailboxes by reference to my module, however Modelsim throws the following error:

A member of a dynamic variable (device_expected_bytes) is not allowed as a port actual.

I don’t understand why this error happens, because I can instantiate the module with

my_module test(.expected_bytes(test));

Any suggestions to this problem would be appreciated!

Thanks!

2

In reply to vemulpt2:

I think the error is incorrect. But here is a workaround

module top;
   parameter NUM_DEVICES = 24;
   
   mailbox #(byte) expected_bytes[NUM_DEVICES];
   
   for(genvar g = 0; g < NUM_DEVICES; g++) begin:device_block
      mailbox #(byte) expected; 
      my_module test(.expected_bytes(expected));
      initial begin
	 expected_bytes[g] = new;
	 expected = expected_bytes[g];
      end
end : device_block
   
endmodule			
 
module my_module(
input mailbox #(byte) expected_bytes
);
endmodule : my_module

Also, there is no need to use a ref port for my_module, the port variable is already a reference.

3

In reply to dave_59:

Thanks for the quick reply Dave, the problem I see with initial block is that I can no longer change the value of “expected”. In some case, I might want to set it to null, so that the module doesn’t write to it. Would there be a way to do that?