Operator Precedence

SystemVerilog
,
1

I have following code ::



   class  Txn ;
 
     static  int  count  ;

             int  id ;

    function  new() ;
      
       `ifdef  POST
          id = count ++ ;
       `elsif  PRE
          id = ++count ;
       `endif

        $display( " id == %0d N count == %0d " , id , count ) ;
     
    endfunction
    
   endclass
  
   module  top_tb ;
   
     Txn  t1 , t2 ;

     initial  begin

       t1 = new() ;
    
       t2 = new() ;
  
     end 

   endmodule

With +define+PRE ::
id == 1 N count == 1
id == 2 N count == 2

With +define+POST ::
id == 0 N count == 1
id == 1 N count == 2

As per the name i.e pre-increment N post-increment , the O/P is as I expected , however I get confused when I look
at LRM 11.3.2 Operator Precedence

**Unary Operator ( ++ ) has a higher precedence than = .

So shouldn’t the RHS be incremented ( for both pre N post increment ) and then assigned to LHS ?**

2

No, the precedence rules do not change the fact that the result of the post-increment operation is always the value before incrementing. The precedence rules only dictate what is being operated on.

id = count ++ ;

is explicitly

id = (count ++) ;

and not

(id = count) ++;