<-> operator need/application

SystemVerilog
1

Hi Dave,
Below code gives same results with == and <->. I am trying to understand the need/application for ↔ operator in constraints.


class test;
  rand bit a,b;
  constraint c1 {
   //a==b;
   a<->b; 
  }
endclass

module tb;
test t_h;
  initial begin
    t_h=new;
    repeat(10) begin
      assert(t_h.randomize);
      $display("%p",t_h);
    end
  end
  
endmodule
2

In reply to verifeng2:

In your simple example, there is no difference. Both operands are self-determined

x <-> y

is equivalent to

(x==0) ~^ (y==0)

Also the ↔ operator has the lowest precedence before assignment and concatenation.

a || b == c || d

gets evaluated as

a || (b == c) || d

whereas

a || b <-> c || d

gets evaluated as

(a || b) <-> (c || d)

This operator is more useful for assertions dealing with true or false expressions.