Nonblocking assignment inside SVA?

SystemVerilog
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1

Hi,

I know one could using assignment to “remember” some state for later checking by using local variable, but what does NBA in SVA do?
I came across this one somewhere but I’m not able to ask the code author.

property ldb_cwf_cnt_check;                                                 
   @ (negedge clk) disable iff (enable_sva == 0 || rst_n == 0)             
      `DUT_PATH.cwf_cnt[6:0] <= `DUT_PATH.cwf_os_number;
endproperty: ldb_cwf_cnt_check                                              
                                                                            
 ldb_cwf_cnt_check_assert: assert property(ldb_cwf_cnt_check);

both signals are rtl dut signals. I’m curious what does this sva do as I seldom see “<=” operator in sva.

Thanks,
Jeff

2

In reply to Jeff_Li_90:

This is not an assignment operator, it is aless-than-or-equal operator. Assignment statements are only allowed in certain places according to the BNF.

3

In reply to dave_59:

oh gees, I feel embarrassed.

Thanks, Dave