Hi,
What will be the output of the following code. Is it possible to apply multiple cont assign on ref ports.
module childMod(input wire logic [31:0] a, output var [31:0] val);
assign val = a + 1;
childMod1 ch2(a, val);
endmodule
module childMod1(a,val);
input wire logic [31:0]a;
ref logic[31:0] val;
assign val = a + 10; //should not allow
always @(val) begin
$display($time(), ": Always [%m] val = %d, a = %d", val , a);
end
endmodule
module top();
logic [31:0] a;
logic [31:0] val;
logic [31:0] r_a;
logic [31:0] r_b;
assign a = r_a;
childMod ch1(a, val);
initial begin
#1 r_a = 10;
end
endmodule