Multiple constraint question

SystemVerilog
1

If I created several constraints like below


class my_trans extends uvm_sequence_item;
  rand bit a;
  rand bit b;
  rand bit c;

  constraint AA {
     a == 1;
  }
  constraint BB {
    b == 1;
  }
endclass

How to enable AA only in my first testcase and enable BB only in my second testcase, and enable all constraints in my others testcase ?

2

In reply to zz8318:

Use the UVM factory to override my_trans with the constraint() you want disabled.

class my_trans_first extends my_trans;
`umm_object_utils(my_trans_first)
constraint BB {};
endclass

In your first test set the override in any phase before run_phase

set_type_override_by_type(my_trans::get_type(), my_trans_first::get_type());
3

In reply to dave_59:

If we have lots of constraint in this my_trans class and each test needs one of them. How to handle it ? We have to create lots of child class which extends my_trans , just like you mentioned ?

4

In reply to zz8318:

Hi ,

You could use constraint_mode as a Task to solve your query



// **In Each Test after creation of my_trans but before randomizing it**

my_trans_object.constraint_mode(0) ; // Used as a Task Will disable all Constraints 

my_trans_object.AA.constraint_mode(1) ; // Used as a Task Will enable Only Constraint AA

I hope this would help you

Regards,
AGIS

5

In reply to Etrx91:

Yes, I saw that in the IEEE document and thanks for your great help