Multidimensional arrays

SystemVerilog
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1

I am trying to understand multidimensional arrays such as this

reg [7:0][3:0] array[2][2]

  1. what does reg [7:0][3:0] mean?
  2. how do I access elements in the array, does this work array[0][0] = '{8’h4,4’h2};array[0][1] = '{8’h5,4’h3}
  3. how do I iterate through the elements using foreach loop, what’s the exact syntax. if someone can provide me a working code that would be great Thanks
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In reply to raja7052:

Ping, Can someone help me with this? Thanks

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In reply to raja7052:

Please see Difference between Packed and UnPacked Arrays | Verification Academy

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In reply to dave_59:

Thanks Dave, that was very helpful