Modelling Jitter and frequency offset in Testbench

SystemVerilog
1

I want to model fractional frequency offset of clock to +/-100ppm
and jitter figure is 2ns peak to peak when measured over a 60sec interval.

How can i model this behavior in my testbench.

2

In reply to ashish_banga:

I want to model fractional frequency offset of clock to +/-100ppm
and jitter figure is 2ns peak to peak when measured over a 60sec interval.
How can i model this behavior in my testbench.

The model below demonstrates a clock with jitters. You need to modify the probabilities and the amount of jitters as you see fit.


import uvm_pkg::*; `include "uvm_macros.svh" 
module m; 
	// I want to model fractional frequency offset of clock to +/-100ppm
    // and jitter figure is 2ns peak to peak when measured over a 60sec interval.
	bit clk, t;  
	 
 	initial forever begin 
	   #29ns if (!randomize(t)  with 
           { t dist {1'b1:=1, 1'b0:=10};
           }) `uvm_error("MYERR", "This is a randomize error")
       if(t) begin // jitter 
          clk=!clk; // early clock flip 
	     end 
	   else #1ns clk=!clk; // normal clock flip 
	   #29ns  if (!randomize(t)  with 
           { t dist {1'b1:=1, 1'b0:=15};
           }) `uvm_error("MYERR", "This is a randomize error")
       if(t) begin 
          clk=!clk;
	      end 
	   else #1ns clk=!clk;
	 end 
 endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

Hi Ben,
Thanks for reply.
But my clk period is 8 ns. Introducing +/- 1ns at one time may be big. How can I distribute it effectively over cycles of clk.

4

In reply to ashish_banga:
My model was intended to demonstrate the concept to introduce jitter.
For lower resolutions, play with the timeunit and timeprecision . You’ll also need to play with the weighted distributions to get the frequencey of occurrences for the jitters.
Hope this helps.
Ben Cohen SystemVerilog.us