hi,
generally verilog is a static memory storage and system verilog is a dynamic memory storage. please explain what is meaning of this
*In reply to nana:*I would not phrase it that way.
In 1986, Verilog started out with only static variables, meaning variables with the lifetime of the full simulation. Fifteen years later, Verilog-2001 added automatic variables. Those are variables with a lifetime coinciding with the activation of a task or function.
SystemVerilog adds a few different kinds of dynamic storage variables. There are variables that can allocate memory based on executing a procedural statement. SystemVerilog has dynamic arrays, queues, associative arrays, and class objects that can all allocate memory executing a statement.
SystemVerilog still has all the static and automatic variables defined in Verilog.
Thankyou for your reply dave_59.
i heard. static means it will allocate memory during compilation time. dynamic means it will allocate memory during run time. is it right?
In reply to nana:
You can think of it that way, but I prefer to say the memory for static variables get allocated and initialized at run-time before time 0.