MACRO for creating object

SystemVerilog
1

I made a macro for creating a UVM object. Currently, the macro accepts two inputs: TYPE and NAME.

`define MAKE_OB(TYPE, NAME) \
  NAME = TYPE::type_id::create("NAME");

...

`MAKE_OB(my_type, t);

I would prefer to only pass NAME. Is there a way to automatically pull the TYPE of the object?

Something like…

`define MAKE_OB(NAME) \
  NAME = PULL TYPE HERE::type_id::create("NAME");
2

In reply to bmorris:

You can do something like:


`define MAKE_OB(NAME) \
  NAME = NAME.type_id::create("NAME");

This works because using ‘.’ is also legal to access static properties (as per 8.9 Static class properties in the LRM).

3

In reply to Tudor Timi:

That’s good information, but that syntax leaves me with:

t = t.type_id::create(“t”);

which causes an error. Is that the format you meant?
Im not interested in much as legal syntax to access a static method, but the proper code to create an object without explicitly supplying the TYPE of object.

my_type t;
`MAKE_OB(t); <---- this alone has enough smarts to create the object, no type given.  how to do?
4

In reply to Tudor Timi:

That won’t work because type_id is a type, not a static method.

In reply to bmorris:

This should do the trick:

`define MAKE_OB(NAME) \
begin \
   typedef type(NAME) NAME``_t; \
   NAME = NAME``_t::type_id::create(`"NAME`"); \
end
5

In reply to dave_59:

I think RivieroPro doesn’t support the type operator. Saw a similar post from 2014 with the same sentiment. bummer!