For loop and fork join in verilog

SystemVerilog
, ,
1 
task forkkk;
begin
    for(i=0; i<3;i=i+1) begin
        fork begin
           begin: thread_0
               if(i==0)
               $display(%d,i);
           end
           begin: thread_1
               if(i==1)
               $display(%d,i);
           end
           begin:thread_2
               if(i==2)
                   $display(%d,i);
           end  

    end
end
join

end

As in systemverilog, I would have to use automatic.

  for( int j = 1; j < 3; ++j ) begin
    fork    
      automatic int k = j; 
      begin         
         $display(k,j);
       end
     join
  end

I want to see what is the difference if i indeed used one of the styles in my driver code, which is to replace the display statement with some other statements.

Currently it seems that the for loop in verilog gives me the same result without automatic.

Besides, should i always use a Nonblocking A to drive inputs? What is the disadvantage of using a blocking assignment if all inputs are exclusively independent(no race condition will happen)? Will the simulator have issues as to sample the signal before the clock edge or after? I sometimes find problems that the simulator sometimes drive my input before the edge and sometimes after it, would it possibly because of my for loop usage is wrong and using blocking assignment?

2

In reply to goodice:

First of all, it doesn’t make sense to discuss fork/join without some time consuming constructs like delays or event controls. Otherwise it behaves the same as begin/end.

But I think the SystemVerilog case, you meant to write fork/join_none. Otherwise each iteration of the for loop must execute serially. When you switch to fork/join_none, that’s when the automatic lifetime is needed.

I think you need to ask a separate question about blocking assignment and show some code.

3

In reply to dave_59:

thank you for your help.

what would be the consequence of using the code in case 1 without time, assume my goal is to drive my input in parallel?Undetermined Race condition?

4

In reply to goodice:

In both cases, Verilog or SystemVerilog, using a fork/join creates a serial execution of the blocks. fork/join is a blocking statement.