Logic values

SystemVerilog
,
1

What does Z in systemverilog stand for?
reg [15:0]Bus;
Bus=zzzzzzzzzzzzzzzz;
What is the meaning of z here?
From the IEEE Std 1800-2017, section “6.3.1 Logic values”:

z—represents a high-impedance state

The SystemVerilog value set consists of the following four basic values:

0—represents a logic zero or a false condition
1—represents a logic one or a true condition
x—represents an unknown logic value
z—represents a high-impedance state

The values 0 and 1 are logical complements of one another.

2

In reply to anvesh dangeti:

I believe you obviously understand what 0 and 1 stand for —

z is used to model/represent high impedance For e.g a shared bus to which nobody is driving
x is used to model/represent there are more than one driver of same strength and most likely driving conflicting values

3

A z value is typically the output of a tri-state buffer (or tri-state inverter) when it is not enabled as a driver. One might use a tri-state buffer to read and write data over the same set of wires.


module tri_state_buffer
(
  input logic enable,
  input logic a,

  output logic y
);
  always_comb begin
    if (enable) begin
      y = a;
    end
    else begin
      y = 1'bz;
    end
  end

endmodule