Lint Errror SV.3 - Assigning 4 state variable to 2 state variable

SystemVerilog
,
1

I am trying to clean up lint error as shown below:
SV.3 Assignments from 4 state to 2 state must include X,Z check


line 0: bit[47:0] da;
line 1: da = packer.unpack_field_int($bits(da));

Line 1 displays the lint error. What is the recommended way to clean up this?

Shall I use $isunknown to check for X/Z and assign da=0 or there is another way to do this.

I would appreciate some insights on this.
Thanks!

2

Line 1, is quite a dangerous assignment, as it “quietly” removes Xs and Zs in the original 4 state variable
without any warning. So $isunknown() check has to be used before this assignment.

The only question what would you do if $isunknown() returns true… Assigning da to 0 is one solution,
but that is equivalent to assigning a bit vector of 48 zeros to da. I would even suggest a $fatal() if
Xs and Zs are found.

3

In reply to logie:

Thank you for the reply.

But the problem I am experiencing with $isunknown() us explained below:


line 0: if($isunknown(packer.unpack_field_int($bits(da)))) begin
line 1:  `uvm_fatal()
line 2: end
line 3: else begin
line 4:  da = packer.unpack_field_int($bits(da));
line 5: end

In the above logic, I need to use two lines for unpacking based on the value of $isunknown(), that actually doesn’t unpack correctly as in the line 0, unpacking is already done but it did not store the value of da. I don’t know what I can do to solve this.