I wish to know how can level triggering be done in Verilog. I am writing contents to a file and I wish to write at Level-Triggering of the clock but I am unable to implement the level triggering. I thought of the following method :
module tb(input clk,
input[31:0] wdata,
input[31:0] addr
);
integer fd;
initial
begin
fd = $fopen("test.txt","w");
forever
begin
wait(clk)
begin
$fwrite(fd,wdata);
$fwrite(fd,addr);
end
end
$fclose(fd);
end
endmodule
Can someone tell me whether it is correct or not or suggest any alternate method to implement level-triggering.
Thank you
PS- If this is right method, should there be a semicolon after wait(clk) or not?