Hi,
I have to write a system verilog layered testbench for a dut combining convolutional encoder of a code rate=1/2 and constraint length=3 and a viterbi decoder such that while giving 8 bit input to the convolutional encoder, I need to get the same 8 bits as the output of viterbi decoder. But since it’s a convolutional encoder it will only take 1 bit input per cycle.
I have written the code but my values in the input of convolutional encoder and in the output of viterbi decoder are not matching.
I’m attaching the system verilog layered testbench and the values of the transcript window.
Here is the complete system verilog code:
//-------------------------------------------------------------------
//Transaction
//-------------------------------------------------------------------
class transaction;
//declaring the transaction items
rand bit ip; //input
bit [7:0]dec_op;//output
function void display(string name);
$display("- %s ",name);
$display("-ip = %b, - dec_op = %b",ip,dec_op);
endfunction
endclass
//-------------------------------------------------------------------
//Generator
//-------------------------------------------------------------------
class generator;
//declaring transaction class
rand transaction trans;
//repeat count, to specify number of items to generate
int repeat_count;
//mailbox, to generate and send the packet to driver
mailbox gen2driv;
//event, to indicate the end of transaction generation
event ended;
//constructor
function new(mailbox gen2driv);
//getting the mailbox handle from env, in order to share the transaction packet between the generator and driver, the same mailbox is shared between both.
this.gen2driv = gen2driv;
endfunction
//main task, generates(create and randomizes) the repeat_count number of transaction packets and puts into mailbox
task main();
repeat(repeat_count) begin
trans = new();
if(!trans.randomize())
//$fatal("GEN::transaction randomization failed");
//assert(trans.randomize())
trans.display("[ Generator ]");
gen2driv.put(trans);
end
-> ended; //triggering indicates the end of generation
endtask
endclass
//---------------------------------------------------------------------------------------
//Interface
//---------------------------------------------------------------------------------------
interface intf(input logic clk,rst1,rst2);
//declaring the signals
logic valid;
logic ip;
logic [7:0]dec_op;
endinterface
//---------------------------------------------------------------------------------------
//Driver
//---------------------------------------------------------------------------------------
class driver;
int no_transactions;
virtual intf vif;
mailbox gen2driv,drv2scb;
function new(virtual intf vif,mailbox gen2driv,drv2scb);
this.vif = vif;
this.gen2driv = gen2driv;
this.drv2scb = drv2scb;
endfunction
task rst;
wait(vif.rst1);
$display("[ DRIVER ] ----- Reset Started -----");
vif.ip <= 0;
vif.valid <= 0;
wait(!vif.rst2);
$display("[ DRIVER ] ----- Reset Ended -----");
endtask
task main;
forever begin
transaction trans;
gen2driv.get(trans);
@(posedge vif.clk);
vif.ip <= trans.ip;
vif.valid <= 1;
@(posedge vif.clk);
vif.valid <= 0;
trans.dec_op = vif.dec_op;
@(posedge vif.clk);
drv2scb.put(trans);
trans.display("[ Driver ]");
no_transactions++;
end
endtask
endclass
//------------------------------------------------------------------------------
//Monitor
//------------------------------------------------------------------------------
class monitor;
//creating virtual interface handle
virtual intf vif;
//creating mailbox handle
mailbox mon2scb;
//constructor
function new(virtual intf vif,mailbox mon2scb);
//getting the interface
this.vif = vif;
//getting the mailbox handles from environment
this.mon2scb = mon2scb;
endfunction
//Samples the interface signal and send the sample packet to scoreboard
task main;
forever begin
transaction trans;
trans = new();
@(posedge vif.clk);
wait(vif.valid);
trans.ip = vif.ip;
@(posedge vif.clk);
trans.dec_op = vif.dec_op;
@(posedge vif.clk);
mon2scb.put(trans);
trans.display("[ Monitor ]");
end
endtask
endclass
//------------------------------------------------------------------------------------
//Scoreboard
//------------------------------------------------------------------------------------
class scoreboard;
mailbox mon2scb, drv2scb;
int no_transactions;
function new(mailbox drv2scb, mon2scb );
this.mon2scb = mon2scb;
this.drv2scb = drv2scb;
endfunction
task main;
transaction trans1,trans2;
forever begin
mon2scb.get(trans1);
drv2scb.get(trans2);
$display("transaction No : %0d", no_transactions+1);
if((no_transactions+1) == 8) begin
if (trans1.dec_op == trans2.dec_op)
$display("Result is as Expected Driver to Scoreboard : %p, Monitor to Scoreboard : %p", trans1, trans2);
else
$error("Wrong Result.\n\tDriver to Scoreboard : %p, Monitor to Scoreboard : %p", trans1, trans2);
end
no_transactions++;
//trans.display("[ Scoreboard ]");
end
endtask
endclass
//----------------------------------------------------------------------------------------
// Environment
//----------------------------------------------------------------------------------------
//`include "transaction.sv"
//`include "generator.sv"
//`include "driver.sv"
//`include "monitor.sv"
//`include "scoreboard.sv"
class environment;
//generator and driver instance
generator gen;
driver driv;
monitor mon;
scoreboard scb;
//mailbox handle's
mailbox gen2driv;
mailbox mon2scb;
mailbox driv2scb;
//virtual interface
virtual intf vif;
//constructor
function new(virtual intf vif);
//get the interface from test
this.vif = vif;
//creating the mailbox (Same handle will be shared across generator and driver)
gen2driv = new();
mon2scb = new();
driv2scb = new();
//creating generator and driver
gen = new(gen2driv);
driv = new(vif,gen2driv,driv2scb);
mon = new(vif,mon2scb);
scb = new(driv2scb,mon2scb);
endfunction
//
task pre_test();
driv.rst();
endtask
task test();
fork
gen.main();
driv.main();
mon.main();
scb.main();
join_any
endtask
task post_test();
wait(gen.ended.triggered);
wait(gen.repeat_count == driv.no_transactions);
//Optional
wait(gen.repeat_count == scb.no_transactions);
endtask
//run task
task run;
pre_test();
test();
post_test();
$finish;
endtask
endclass
//------------------------------------------------------------------------------------
//Random test
//------------------------------------------------------------------------------------
program test(intf i_intf);
//declaring environment instance
environment env;
initial begin
//creating environment
env = new(i_intf);
//setting the repeat count of generator as 8, means to generate 8 packets
env.gen.repeat_count = 6;
//calling run of env, it interns calls generator and driver main tasks.
env.run();
end
endprogram
//-------------------------------------------------------------------------------
// testbench
//-------------------------------------------------------------------------------
module testb_top;
//clock and reset signal declaration
bit clk;
bit rst1;
bit rst2;
//clock generation
always #5 clk = ~clk;
//reset Generation
initial begin
rst1 = 1;
#5 rst1 =0;
end
initial begin
rst2 = 1;
#5 rst2 =0;
end
//creatinng instance of interface, inorder to connect DUT and testcase
intf i_intf(clk,rst1,rst2);
//intf i_intf(clk,rst2);
//Testcase instance, interface handle is passed to test as an argument
test t1(i_intf);
//DUT instance, interface signals are connected to the DUT ports
combined DUT (
.clk(i_intf.clk),
.rst1(i_intf.rst1),
.rst2(i_intf.rst2),
.ip(i_intf.ip),
.dec_op(i_intf.dec_op)
);
endmodule
I’m also attaching the output I got.
[ DRIVER ] ----- Reset Started -----
# [ DRIVER ] ----- Reset Ended -----
# - [ Driver ]
# -ip = 0, - dec_op = 00000000
# - [ Monitor ]
# -ip = 0, - dec_op = 00000000
# transaction No : 1
# - [ Driver ]
# -ip = 1, - dec_op = 00000000
# - [ Monitor ]
# -ip = 1, - dec_op = 00000000
# transaction No : 2
# - [ Driver ]
# -ip = 0, - dec_op = 00000000
# - [ Monitor ]
# -ip = 0, - dec_op = 00000000
# transaction No : 3
# - [ Driver ]
# -ip = 1, - dec_op = 11100000
# - [ Monitor ]
# -ip = 1, - dec_op = 11100000
# transaction No : 4
# - [ Driver ]
# -ip = 1, - dec_op = 11100000
# - [ Monitor ]
# -ip = 1, - dec_op = 11100000
# transaction No : 5
# - [ Driver ]
# -ip = 1, - dec_op = 11100000
# - [ Monitor ]
# -ip = 1, - dec_op = 11100000
# transaction No : 6
# - [ Driver ]
# -ip = 1, - dec_op = 11100000
# - [ Monitor ]
# -ip = 1, - dec_op = 11100000
# transaction No : 7
# - [ Driver ]
# -ip = 1, - dec_op = 11100000
# - [ Monitor ]
# -ip = 1, - dec_op = 11100000
# transaction No : 8
# Result is as Expected Driver to Scoreboard : '{ip:1, dec_op:224}, Monitor to Scoreboard : '{ip:1, dec_op:224}
# ** Note: $finish : C:/Users/HP EC0036AU/Documents/Project/synt-corr-1_tb/Main Code/eg.sv(383)
# Time: 245 ns Iteration: 1 Instance: /testb_top/t1
Thanks in advance