Is it always necessary to use create() method to instantiate objects in UVM?

SystemVerilog
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1

I have realized that it is always necessary to use create method to instantiate objects in uvm? could someone throw more light on this topic since not much content was found on the web regarding the same

2

In reply to yr:

Yes, you should always use create() since this call utilizes the UVM factory and is a key part of the UVM methodology which allows you to override component types.

3

In reply to cgales:

Ok cgales! I will make a note of that! Thank you!