Issue with Variable Part Select in Constraints

SystemVerilog
,
1

I have following Constraint ::


class MAIN  #( int WIDTH = 32 , int PWIDTH = 4  ) ;

  rand bit [0:(WIDTH-1)] b1   ;
  rand bit [(WIDTH-1):0] b  ;

  int unsigned N  ;          //  Changed @ run-time by user !!

  bit [ (PWIDTH-1):0] ptrn ; // Changed @ run-time !!

  constraint PP  {
                        foreach(b1[i]) // Iterates from MSB (0) to LSB !!
		   if ( i <= ( WIDTH - PWIDTH ) ) // NOTE :: To avoid Out-of-Bound range !!
	         {	      
                      
   ( & ( b[i+:PWIDTH] ~^ ptrn ) ) == ( b1[i] == 1 ) ; // Reduction AND of ( XNOR of 2 Variables ). If both Variables are same its :: ( & ( 4'b1111 ) ) 
                                                      // i.e 1'b1
          
		 }
		  else
		 {
                    b1[i] == 0 ; // No Pattern Match , hence bit would be 0 !!

		 }   
                   
                    $countones(b1) == N ; 
                }


function void post_randomize() ;
  $display("b is %b ",b ) ;
  $display("b1 is %b",b1) ;
endfunction

endclass

module MOD ;

MAIN #(32,4) p1 ;


initial begin

p1  = new() ;

// All ones
 p1.N    = 29 ;
 p1.ptrn = 4'b1111 ;

if ( p1.randomize() )
 begin
   $display("Success with 'b%4b occurring %0d Times ",p1.ptrn,p1.N);
 end

// All zeroes
 p1.N    = 29 ;
 p1.ptrn = 4'b0 ;

if ( p1.randomize() )
 begin
   $display("Success with 'b%4b occurring %0d Times ",p1.ptrn,p1.N);
 end

 p1.N    = 2 ;
 p1.ptrn = 4'b1010 ;

if ( p1.randomize() )
 begin
   $display("Success with 'b%4b occurring %0d Times ",p1.ptrn,p1.N);
 end

end

endmodule

I see following message “The expression this.b[i+:this.PWIDTH] is not supported in constraints.”

Is Variable Part Select restricted in Constraints ?

2

In reply to ABD_91:

This is very likely a simulator-specific limitation, not something prohibited by the LRM.