Issue with typedef enum

SystemVerilog
, ,
1

Hello all,

I’m new to SV and I encountered this error while learning about enums.
I understand that default data type of enum is int. But I’m not sure what is happening here.
Pardon my innocence! Hope you can help me out.

In code::1 I am obtaining the expected result
In code::2 Result is not as I expected

code::1 → 

module enum_work;

  //typedef enum integer {A, B, C} alphabets; 
  typedef enum {A, B, C} alphabets;
  typedef enum {ADD, SUB, MUL, DIV, MOD} math_operations;

  alphabets alpha;
  math_operations math;
  integer i;
 
  initial begin
    i = alpha;
    $display("default alpha value - %d",alpha);
    i++;
    alpha = alphabets'(i);
    $display("incremented alpha value - %d",alpha);
  end
endmodule

This is the output of code::1
default alpha value - 0
incremented alpha value - 1

code::2 → 

module enum_work;

  typedef enum integer {A, B, C} alphabets; 
  //typedef enum {A, B, C} alphabets;
  typedef enum {ADD, SUB, MUL, DIV, MOD} math_operations;

  alphabets alpha;
  math_operations math;
  integer i;
 
  initial begin
    i = alpha;
    $display("default alpha value - %d",alpha);
    i++;
    alpha = alphabets'(i);
    $display("incremented alpha value - %d",alpha);
  end
endmodule

This is the output of code::2
default alpha value - x
incremented alpha value - x

2

In your code:1, you didn’t mention data type of the enumeration. So it will be considered as an “int” data type. int is the default data type of enumeration in the absence of a data type declaration.

int is a 2-state data type whose default value will be 0. On incrementing, it is displayed as 1.

Coming to the code:2, Data type of the enumeration is declared as integer whose default value would be 'x. Hence all x’s in your output

3

In reply to SwaroopKrishna:

Rather than using i++, variables of an enumerated type have a built-in .next method that returns the next value:

alpha = alpha.next;