Interface scope

SystemVerilog
1

Followings it create two module MODULE_1th and MODULE_2th to operate DataA and DataB defined in interface IN_DATA_IF,
I am wondering in MODULE_2th, it didn’t connect top_data_if from port, but MODULE_2th still can recognize the data out of its scope.
Is IN_DATA_IF top_data_if a globe object ?

/* ====================================== */
interface IN_DATA_IF
  logic     [11:0]  DataA ;
  logic     [11:0]  DataB ;
endinterface: IN_DATA_IF
/* ====================================== */
 
/* ====================================== */
module MODULE_1th (
    IN_DATA_IF      data_if,
    output   [11:0] C
    );
    assign C = data_if.DataA + data_if.DataB;
endmodule //DATA_MODULE
/* ====================================== */

/* ====================================== */
module MODULE_2th (
    output   [11:0] C
    );
    logic C;
    assign C = top_data_if.DataA + top_data_if.DataB;
endmodule //DATA_MODULE
/* ====================================== */

 
module top_bench;
  logic   clk, rst;
  IN_DATA_IF top_data_if;
  top_data_if.DataA = 10;
  top_data_if.DataB = 20; 
 
  MODULE_1th(
              .data_if(top_data_if()),
              .C(C_1th)
             );

  MODULE_2th(
              .C(C_2th)
             );

  if (C_1th != C_2th)
  begin
     $display("C_1th and C_2th mismatch");
  end
endmodule //top_bench
2

In reply to vatics_r89162:

This is because of OOMR, out-of-module reference.
As to how to resolve OOMR, read SystemVerilog LRM.
**I forgot the section of LRM.

3

In reply to kitanisi:

Thanks for ur kindly reply. I would check it out.