Is interface mandatory to use?

SystemVerilog
1

Hi Dave,

If there is a situation where i have to sync up my scoreboard with DUT based on some signals, i can certainly tap them using their hierarchical path. Though the recommended way is to use interface. What is that reason we should be using (virtual)interfaces for signal connections anywhere in a testbench and not other ways like i mentioned above?

Regards

2

There is a much simpler way using abstract or interface classes.

See

http://www.doulos.com/downloads/events/DVCon_08_abstractBFM_final.pdf

https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection

http://events.dvcon.org/2015/proceedings/papers/04P_19.pdf

3

In reply to dave_59:

Thanks Dave.