Interface inside interface

SystemVerilog
1

Hi Forum,
In my env I have 2 interfaces.
I need to create 3rd interface which contains the 2 (for mutual assertion reasons).
How do I make the 2 interface inside the 3rd interface point to interface 1 and 2;

This is what I am trying to do but is not working


interface inf_a;
   logic a;
endinterface

interface inf_b;
   logic b;
endinterface

interface inf_c;
   inf_a m_inf_a();
   inf_b m_inf_b();
endinterface

module test;
   inf_a m_inf_a();
   inf_b m_inf_b();
   inf_c m_inf_c();
   initial begin
      m_inf_c.m_inf_a = m_inf_a;
      m_inf_c.m_inf_b = m_inf_b;
   end

endmodule
2

O.K friend explained.
Because it is an interface you have to declare the additional interface in the port list.


interface inf_a;
   logic a;
endinterface
 
interface inf_b;
   logic b;
endinterface
 
interface inf_c(inf_a m_inf_a, inf_b m_inf_b);
endinterface
 
module test;
   inf_a m_inf_a();
   inf_b m_inf_b();
   inf_c m_inf_c(.m_inf_a(m_inf_a), m_inf_b(m_inf_b));
endmodule