I just have a look at some e-books on SVA, but it is too much for me to write interface assertion alone, so I am wondering to what extent I should know about assertions just for time-bound tasks.
I will appreciate it if you can point out the detailed sections of certain SVA book that I should pay close attention to.
In reply to Marina.Miao:
… to what extent I should know about assertions just for time-bound tasks.
I will appreciate it if you can point out the detailed sections of certain SVA book that I should pay close attention to.
The most important concepts that one need to understand about assertions include the following: (section/page references are from my SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
// SVA assertion
ap_ab_then_c : assert property(@(posedge clk)
$rose(a) ##2 b |-> ##3 c);
// The model for the property
task automatic t_a2b_then_3c();
if($rose(a)) begin : rose_a
repeat(2) @(posedge clk); // can use ##2 instead
if(b) begin : got_b
repeat(3) @(posedge clk);
if(c) `uvm_info (tID,$sformatf("%m : AB_then_C PASS, c= %b", c), UVM_HIGH)
else `uvm_error(tID,$sformatf("%m : AB_then_C FAIL @ c= %b", c))
end : got_b
else return; // vacuous assertion, exit task
end : rose_a
endtask
// (file http://SystemVerilog.us/vf/abc_emul.sv)
// Emulating the firing the assertion
always_ff @(posedge clk) begin // emulate the assertion firing
fork
t_a2b_then_3c();
join_none
end
In the assertion @(posedge clk) $rose(a) ##2 b |-> ##3 c); and from the SystemVerilog model you can see the following
Of course, other concepts and examples of SVA provide the user a better understanding on how to apply SVA for your specific verification applications, I provide a lot of this throughut the book, particularly in 5 CHECKER, 6.9 CASE STUDY - SYNCHRONOUS FIFO, 7.3 CASE STUDY - FV OF A TRAFFIC LIGHT CONTROLLER, 10 Assertions Dictionary.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr