Initialize a variable with minimum value

SystemVerilog
1

Hi,

if I want to initialize a signed variable with minimum value (minimum negative value), how can i do it in systemnverilog ?

in C language, i used to do as below:
int x = INT_MIN;

Thanks,
Amit

2

In reply to sv_uvm_learner_1:

Unlike in C, int is a fixed size 32-bits. So you can do

let INT_MIN = 32'sh800000000;