Infinite traces in a given proof

SystemVerilog
,
1

If there is a cover that is just written as below

cover property ( @( posedge clk ) disable iff (reset)
1’b1

What is the explanation for such property?
Is it trying to verify that the proof is having infinite traces possible and thus help in getting more confidence on the liveness properties in the proof?

2

In reply to rrkk66418:
I can see no reason for a cover property like this other than something tool specific.