Import package error

SystemVerilog
, ,
1

Hello,
I have a few packages that I have written like this:

package A;
  -- 
  --
  endpackage 

  package B;
  import A::*
  ---
  -- 
  endpackage

  package C;
  import A::*;
  import B::*;
  endpackage

In the file using package C, the error I am getting is as follows:
Error (10864): SystemVerilog error at C.sv(26): TMP was imported from multiple packages with ::* - none of the imported declarations are visible.

Is this problem because I am importing A::* in both package A and package C?
Any help to resolve this is greatly appreciated.

Thanks in Advance~

–
Nikhil Pratap

2

In reply to nikhilghanathe:

If TMP is only defined in package A, this should not be a problem. Can you show us a Minimal Complete example showing all the places TMP is declared, and then all the places it is referenced.