Import declaration in SV/UVM

SystemVerilog
1

Hi

What is the difference between import package at compilation unit and module header/


``` verilog
import pkg::*;

module A (port);
endmodule A

module A (port);
  import pkg::*;
endmodule A





Which one is preferred why ? Please help 

Regards,
Mehanic
2

In reply to Mechanic:

There is no difference if each module gets compiled into a separate compilation unit and the port declarations need nothing from the package.

But as soon as you introduce multiple packages and multiple modules compiled into the same unit, the unit get “polluted” with multiple package imports. Suppose the following code is compiled into a single unit.

package p1;
  parameter A = 1;
  parameter B = 1;
endpackage
package p2;
  parameter A = 2;
  parameter B = 2;
endpackage

import p1::*;
module m1;
  initial $display("%m.A",,A); //1st reference to A imports p1::A
endmodule

import p2::*;
module m2;
  initial $display("%m.A",,A); // references imported p1::A
  initial $display("%m.B",,B); // B has yet to be imported error, p1::B or p2::B

endmodule

Since module m1 causes an import of p1::A, the import p2::* statement has no effect. A has the value 1. But the 1st reference to B happens after the wildcard import of both p1 and p2. That generates an error.

If your port declarations need data types or parameters from a package, you can explicitly reference the package, or embed the import statement in the module decharation header

package p1;
  parameter A = 1;
  parameter B = 1;
endpackage
package p2;
  parameter A = 2;
  parameter B = 2;
endpackage

module m1 import p1::*; (input logic [A:0] port1, logic [p2::B:0] port2);
  initial $display($bits(port1),, $bits(port2));
endmodule

p1 has been wildcard imported into module m1, and p2::B is an explicit package reference.