Illegal value (14) for ref formal (base). Value must be assignable

SystemVerilog
,
1

I am getting the above compile time error where call to function is made.

The function and caller code looks like below:

function init_array (ref int arr[], int base, int count);
     arr = new [count];
     for (int idx = 0; idx < count; idx++) begin
       arr[idx] = base + idx;
     end
endfunction

calling code:

   init_array (temp, 14, 120);

So, I thought the error is due to the fact that the function expects int base and count variables as inputs but I am passing constants as the input. So, I tried the following example but I don’t see any error in the example code.
The example code runs fine.

module x;
  initial
    begin
      manipulate (10);    
    end
  function manipulate (int num);
    $display ("%d ", num);
  endfunction
endmodule
2

In reply to verif_learner:

The implicit default argument direction is input only for the first argument. The successive arguments use the preceding argument’s direction as the implicit default.