Ignoring array of bins in cross

SystemVerilog
, ,
1

Suppose I have the coverpoints and crosses shown in the code below. Can you please let me know why is my code not working and any alternative that I could try.


bit[31:0] ro_reg_addr[2] = {'h0008_0000,'h0008_000C};
covergroup my_covergroup;
    my_data: coverpoint data {
      bins data[] = {4'ha,4'hb,4'hc};
    }
    example_covpoint: coverpoint addr {
      bins address['h4] = {['h0008_0000:'h0008_000F]};
    }
    my_cross: cross example_covpoint , my_data {
      ignore_bins ro_regs = (binsof(example_covpoint) intersect ro_reg_addr && binsof(my_data) intersect {'hb,'hc}) //-> Doesn't work
      //ignore_bins ro_regs = (binsof(example_covpoint) intersect {ro_reg_addr} && binsof(my_data) intersect {'hb,'hc}) -> Doesn't Work
      //ignore_bins ro_regs = (binsof(example_covpoint) intersect {ro_reg_addr[0],ro_reg_addr[1]} && binsof(my_data) intersect {'hb,'hc}) -> Works fine
      //ignore_bins ro_regs = (binsof(example_covpoint) intersect {'h0008_0008,'h0008_000C} && binsof(my_data) intersect {'hb,'hc}) -> Works fine
endgroup
2

this might be because each bin of example_coverpoint is a range of 4 values ?
why are you clubbing 4 addresses in 1 bin?

3

In reply to sohan_b:

Hi Sohan,
Please check my last comment. That is working fine. I just want to know why can’t I use an array instead of explicitly mentioning individual addresses. The example I shared above is giving compilation errors.

why are you clubbing 4 addresses in 1 bin?

These addresses are for registers (32 bits) in a byte addressed memory. So, 0008_0000 - 0008_003 belongs to single register.

4

Can anybody help me out?

5

In reply to kavish.ahmad1:

The intersect clause allows limited expressions. You want the with clause

ignore_bins ro_regs = (binsof(example_covpoint) with (example_coverpoint inside {ro_reg_addr} && binsof(my_data) intersect {'hb,'hc}) //-> Doesn't work

See 19.6.1.2 Cross bin with covergroup expressions in the 1800-2017 LRM