I want to remove the warning "" so iam trying below code. it's giving syntax error. can you please help me to fix the issue

SystemVerilog
,
1

in below code i want to get the number of bits value and assign that count of “0” to a . but it is giving syntax error.

module top();
  bit [25:0] a;
  bit [8:0] b;
initial
  begin
    $display("hello");
    a=($bits(a)-$bits(b))'b0;
    $display("%d",a);
    $finish;
  end
endmodule

error:
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 10: token is ‘0’
a=($bits(a)-$bits(b))'b0;
^

2

In reply to srikanth.srivishnav:

I don’t understand how the variable b fits into what you want to do. You can just write

a = 0;

and the whatever expression you have on the RHS of an assignment gets 0 extended to fill the LHS. Maybe you can give some other examples of what you are expecting for the value of a.

3

i am planning to change the logic which is needed for my TB. the below example can be explain the working and non-working code.

bit [25:0] a;
bit [8:0] b;

a = {18’h0, b[7:0]}; // working code

same thing i want to change the logic in terms of $bits() it is giving syntax error.

a={($bits(a)-$bits(b))'b0, b}; // syntax error code.

expecting above changed logic should be as a= {17’b0,b}; but it’s giving syntax error.

4

In reply to srikanth.srivishnav:

Again, there is no need to 0 extend unsigned data types

a = b[7:0]; //is equivalent to 

a = {18'b0,b[7:0]};

But if you insist, you can use the replication in concatenation operator.

 a = {{$bits(a)-$bits(b){'0}},b};